AlGaN/GaN-based metal–insulator–semiconductor high electron mobility transistor (MIS-HEMT), presenting a lower gate leakage and a larger gate bias swing than the Schottky HEMT,^[1] is an excellent candidate for power switching application due to the advantages of high speed and high breakdown voltage.^[2,3] However, the non-native gate dielectric will bring bulk defects and interface-states, which will lead to severe reliability issues during the fast switching. Bias temperature instability (BTI), time-dependent dielectric breakdown (TDDB), and stress-induced leakage current (SILC) are hot issues for evaluating the quality of gate dielectric.^[4–6] Positive bias is often necessary to realize the fully turn-on of a MIS-HEMT. However, the long term degradation of electrical parameters during positive gate voltage stress will influence the operation condition. Therefore, an extensive investigation on the positive bias temperature instability (PBTI) is necessary.

To date, some investigations have been performed concerning the gate insulator material, the deposition method of insulator, the AlGaN barrier thickness, etc. Lagger et al. evaluated the threshold voltage (V_th) shift and interface trap density by adjusting the dielectric material and thickness. The capacitance–voltage (C–V) analysis revealed that the density of trapped electron depends on the dielectric capacitance and the gate bias.^[7] He et al. compared the V_th instability of the fully recessed MIS-FET with that of the partially recessed MIS-HEMT. Similar PBTI behaviors were observed for both devices under the positive gate bias stress (V_gstress), but the MIS-FET presents enhanced pulse-mode stability because the fully recessed structure conduces to merging the dielectric/nitride interface with the GaN channel.^[8] Generally, the channel electrons are captured by the interface traps at the dielectric/nitride interface when a positive gate bias is applied, resulting in the PBTI behavior occurring. However, the overdrive gate bias (V_overdrive = V_gstress – V_th) is relatively small in previous studies (below 10 V).^[9,10] Unlike the single dielectric/GaN interface structure in MIS-FET, MIS-HEMT has multiple interfaces below gate dielectric. Therefore, a high overdrive gate bias is necessary to isolate the dielectric/nitride interface for better understanding the PBTI kinetics in GaN MIS-HEMTs.

In this work, PBTI behavior of GaN MIS-HEMT with LPCVD-SiN_x gate dielectric was evaluated under V_overdrive = 18.5 V–25.5 V. The degradation of g_max and SS as a function of ΔV_th are used to evaluate the effect of the overdrive voltage. Besides, the interface state density before and after stress were measured by frequency dependent conductance method. The corresponding degradation kinetics of PBTI reflected by energy band diagram was exhibited based on the experimental and simulation results.

Figure 1 shows the optical photo and the cross-section sketch of the device, which was manufactured on the standard CMOS (complementary metal–oxide–semiconductor) production line. The GaN epitaxial layer was grown by metal organic chemical vapor deposition on a 6-inch (111) Si substrate (1 inch = 2.54 cm), which consists of a 4-μm GaN buffer, a 300-nm/25-nm AlGaN/GaN heterojunction and a 2-nm GaN cap. Sandwiched between the AlGaN/GaN heterojunction is a 0.7-nm AlN interlayer.

Fig. 1.

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	Fig. 1. (a) Micro-photograph and (b) schematic cross-section of GaN MIS-HEMT with LPCVD SiNx dielectric.

The device process started with a 300-nm mesa etching, then a 35-nm SiN_x was deposited by low pressure chemical vapor deposition (LPCVD) as the first passivation layer as well as the gate dielectric on the top GaN, followed by a second passivation layer of 500-nm SiO₂ obtained by plasma enhanced chemical vapor deposition. Then, two 560-nm depth windows were opened by a combination of inductivity coupled plasma (ICP) dry etching and wet etching method for source and drain ohmic contact, and a 20-nm/120-nm/70-nm/60-nm Ti/Al/Ti/TiN metal was deposited by physical vapor deposition, then a rapid thermal annealing process was performed under 850 °C at N₂ environment for 45 s. Followed closely was the gate window opened and gate metal deposition process by using the TiN/Ti/Al with the thickness of 20 nm/30 nm/100 nm. The device used in this work features a dimension of L_g/L_gs/L_gd/W_g at 3 μm/3.5 μm/6.5 μm/100 μm.

Before stress tests, all devices were initialized by a negative gate bias (V_g = –1.5 V) pre-treatment, with the source and drain grounded (V_s = V_d = 0 V) for 1000 s. Then the initial electrical parameters, such as threshold voltage V_th0 = − 10.5 V (defined at I_d = 1 mA/mm), maximum trans-conductance (g_max0) of 5.46 mS/mm, and subthreshold swing (SS₀) of 80 mV/dec were extracted as reference values for subsequent stress experiments (Fig. 2(a)). The aim of pre-treatment is to release the electrons from the pre-existing trapping sites to realize initial stabilization. Based on the time dependent dielectric breakdown (TDDB) tests, the gate voltage for lifetime of 10 years is about 15 V as shown on the curve of the scale factor (η) of 63.2% (Fig. 2(b)). This value is regarded as a maximum gate voltage stress in the following PBTI tests.

Fig. 2.

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	Fig. 2. (a) Transfer characteristics after a pretretment under Vg = −1.5 V, Vs = Vd = 0 V, 1000 s. (b) Before PBTI tests, an extrapolated lifetime of TDDB versus gate bias shows that the gate voltage on the curve of TDDB scale factor (η) of 63.2% at 10 years is about 15 V.

The PBTI test (including two segments of stress phase and recovery phase) is a static measure/stress/measure test under different values of constant gate voltage and temperature stressed. In the stress phase, devices were biased under a constant static positive gate voltage stress (V_gstress) and V_s = V_d=0 V for different stress times. After every stress phase, a gate recovery voltage of −1.5 V was given immediately also with V_s = V_d = 0 V. During all stress phases and recovery phases, fast I_d–V_g sweeps (about 1 s–2 s) were obtained for monitoring the evolution of V_th, g_max, and SS at 10 s, 30 s, 60 s, 100 s, 300 s, 600 s, 1000 s, respectively. The gate leakage current was also recorded at each measurement, showing no obvious variation even with the maximum stress voltage V_gstress = 15 V and highest temperature of 125 °C for 1000 s (not shown).

In summary, a comprehensive investigation of high overdrive voltage on PBTI ctrapping behavior is presented for D-Mode GaN MIS-HEMTs with LPCVD-SiN_x gate dielectric. A higher overdrive voltage is more effective to accelerate the electron trapping process, and introduces new interface/border defects in the dielectric, thus the spread of empty dielectric traps above the channel Fermi level will become wider, and the concentration of traps will become closer to the channel Fermi level, resulting in a higher trapping probability, hence a larger ΔV_th with a weaker time dependence and a weaker temperature dependence are observed.